powerpc em603e and 603e microprocessors optimized for embedded applications highlights powerpc em603e * and 603e family processors are 32-bit implementations of the powerpc reduced instruction set computer (risc) microprocessor family. they offer high clock frequency and efficient throughput driven by five execution units and the ability to issue and retire t wo instructions per clock. although all models provide industry- leading value because of a low-cost manufacturing process, em603e models can provide even greater value in applications which do not need floating- point functionality. all powerpc em603e and 603e proces- sors are price-positioned and function- ally optimized for the high-end embed- ded market, making them ideal for networking and communications applications. summary of features: power management unit ? low-power design ? dynamic power management ? doze, nap, and s leep power savings modes ? 3.3v or 2.5v core power supply available instruction fetching & branch unit ? 6-instruction prefetch queue ? static branch prediction dispatch unit ? dispatches 2 instructions per cycle ? 4-stage pipeline: fetch, dispatch, execute, and complete load/store unit ? one cycle cache access ? executes cache and tlb instructions ? alignment and number denormalization ? hit under reload instruction fixed-point execution unit ? one cycle add, subtract, shift, or rotate ? hardware multiply and divide ? thirty-two, 32-bit general purpose registers floating-point execution unit (powerpc 603e only) ? optimized for single-precision multiply/add ? ieee-754 standard single-and double- precision floating point arithmetic ? thirty-two, 64-bit floating point registers system unit ? executes condition register logical, special register transfer, and other system instructions ? executes integer add/compare instructions memory management unit ? 52-bit virtual and 32-bit real addressing ? 8 block address translation registers ? 64-entry, 2-way data and instruction tlb ? fast-trap mechanism for software reload tlb cache unit ? 16k, 4-way set associative instruction cache ? 16k, 4-way set associative data cache ? 3-state hardware coherency (mei); compatible with four-state mesi protocol ? physically tagged and addressed ? copy-back data cache ? hardware support for data coherency bus interface unit ? general purpose interface for a wide range of system configurations ? 32-bit address and selectable 64- or 32-bit data bus ? powerful diagnostic and test interface through the common on-chip proces- sor (cop) and ieee 1149.1 (jtag) interface ? parity checking on bus ? fast reset due to level sensitive scan design (lssd) ? bi-endian operation
*07gk21026200* g gk21-0262-00 ? international business machines corporation 1998 printed in the united states of america 1-98 all rights reserved * indicates a trademark or registered trademark of the international business machines corporation. ** all other products and company names are trademarks or registered trademarks of their respective holders. the information contained in this document is subject to change wi thout notice. the products described in this document are not intended for use in implanta- tion or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibms product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all the information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. the information cont ained in this document is provided on an as is basis. in no event will ibm be liable for any damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6531 the ibm home page can be found at: http://www.ibm.com the ibm microelectronics division home page can be found at: http://www.chips.ibm.com powerpc em603e and 603e specifications processor speed processor speed processor speed processor speed processor speed 100, 166 and 200 mhz technology technology technology technology technology 100 mhz 0.5m/0.46m l eff , cmos, 4 levels metal 166 mhz 0.35m/0.25m l eff , cmos, 5 levels metal 200 mhz 0.35m/0.18m l eff , cmos, 5 levels metal die size die size die size die size die size 100 mhz 8.4 mm x 11.67 mm (98 mm 2 ) 166/200 mhz 7.5 mm x 10.5 mm (79 mm 2 ) 100 mhz (603e) 120 specint92, 105 specfp92 100 mhz (em603e) 120 specint92, or 135 dhrystone 2.1 mips performance performance performance performance performance (est.) 166 mhz (603e) 4.1 specint95, 3.0 specfp95 166 mhz (em603e) 4.1 specint95, or 225 dhrystone 2.1 mips 200 mhz (603e) 5.1 specint95, 3.7 specfp95 200 mhz (em603e) 5.1 specint95, or 271 dhrystone 2.1 mips cpu bus ratio cpu bus ratio cpu bus ratio cpu bus ratio cpu bus ratio 100 mhz 1x, 1.5x, 2x, 2.5x, 3x, 3.5x, 4x 166/200 mhz 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x signal i/os signal i/os signal i/os signal i/os signal i/os 165 power supply power supply power supply power supply power supply 100 mhz 3.3v +/- 5% i/o, 3.3v +/- 5% core 166/200 mhz 3.3v +/- 5% i/o, 2.5v +/- 5% core 100 mhz 3.2w typical power dissipation power dissipation power dissipation power dissipation power dissipation (est.) 166 mhz 3.0w typical 200 mhz 4.0w typical temperature range temperature range temperature range temperature range temperature range 0c to 105c packaging packaging packaging packaging packaging 100/166/200 mhz 255-pin cbga 100 mhz 240-pin pqfp powerpc em603e and 603e block diagram instruction fetch and branch unit system unit dispatch unit integer unit load-store unit floating point unit bus interface unit cop/jtag unit instruction mmu i-cache int. reg. file fp reg. file 32 address data 64 64 64 64 32 or 64 64 64 64 32 data mmu d-cache (603e only)
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